Certain Investigations on Static Power Dissipation in various Nano-Scale CMOS D Flip-Flop Structures

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Author(s) R.Udaiyakumar | K. Sankaranarayanan
Pages 644-652
Volume 2
Issue 4
Date April, 2012
Keywords CMOS, MOSFET, D Flip Flop, Leakage current, Forced Transistor Stack, Multiple Threshold, Super-Cutoff

Abstract

In this paper the impact of existing leakage current reduction techniques on Various D Flip Flop Circuits are analyzed and summarized. As Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices are scaled down to nanometer ranges, Complementary MOS (CMOS) circuit’s total Power consumption has a new definition. Due to integration of millions of components and shrinking process technology, nowadays leakage power tends to play a major role in total power consumption. This fact has motivated a lot of researchers and technologists to choose leakage current minimization as their future work. This paper explores various D flip-flop topologies meant for different constraints such as speed, area and power. Proper selection of flip-flops is necessary in order to satisfy low power and high performance circuit. In this paper, different flip flop circuits are designed using 16nm Metal gate, High-K dielectric, Silicon on Insulator (SOI) Low Power Predictive Technology Model (PTM) file developed based on Berkeley Short Channel Insulated Gate MOSFET (BSIM) model equations. As the estimation of leakage at circuit level is of prime importance for VLSI engineers, this paper aims at implementation of both active and standby mode leakage power reduction techniques. Of the available techniques, six techniques are considered for the purpose of analysis namely Multi Threshold CMOS (MTCMOS), Super Cut-off CMOS (SCCMOS), Forced Transistor Stacking (FTS) and Sleepy Stack (SS). From the results, it is observed that MTCMOS and SCCMOS techniques produces lower power dissipation than the other techniques due to the ability of power gating. As there were no previous works reported related to comparison of power analysis of 16nm devices with the above leakage reduction techniques, in this paper a qualitative comparison is done with the help of TannerSPICE Circuit Simulation Tool. After a detailed analysis of the existing techniques, this paper concludes that same leakage reduction technique produce different power optimization levels for different architectures and employing a suitable technique for a particular architecture will be an effective way of reducing the leakage current and thereby static power.

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