Design of Analog VLSI Architecture for DCT

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Author(s) M.Thiruveni | M.Deivakani
Pages 1475-1481
Volume 2
Issue 8
Date August, 2012
Keywords Sample and Hold, Discrete Cosine Transform, Discrete Fourier Transform, Discrete Sine Transform, Discrete Hartley Transform


When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and round off noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of the analog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach of analog CMOS implementation technique for Digital Signal Processing (DSP) algorithms to reduce the area and power requirement in the existing Digital CMOS implementations. Discrete Cosine Transform (DCT) with signed coefficients have been designed and implemented in this paper. The problems of digital DCTs viz., quantization error, round-off noise, high power consumption and large area are overcome by the proposed implementation. It can be used to develop the architecture design of DFT, DST and DHT.

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