Power Optimization of AHB Slave-SPI Master with RTL Clock Gating

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Author(s) Chetan Sharma | Abhishek Godara
Pages 343-346
Volume 2
Issue 3
Date March, 2012
Keywords SPI (Serial Peripheral Interface), MOSI (Master Out Slave In), MISO (Master In Slave Out), SCLK (SPI Clock), SS (Slave Select) AMBA (Advanced Microcontroller Bus Architecture), AHB (Advanced High Performance Bus), RTL (Register Transfer Level), FPGA (Field Programmable Gate array).
Abstract

SPI (Serial Peripheral Interface) is a serial interface which facilitates the synchronous serial data transfer between 2 devices. It operates in master and slave modes. AMBA (Advanced Microcontroller Bus Architecture) is an on chip bus developed by ARM Ltd. and is widely used in Soc designs. AHB (Advanced High Performance Bus) is a high frequency and high bandwidth bus which comes under AMBA classification. The AMBA-AHB slave interface programs the SPI registers. In this paper the power consumption of AHB SPI-Master is being optimized by using RTL clock gating technique. The RTL clock gating technique is used for reducing dynamic power consumption. The overall design comprises of AHB- slave interface, SPI-master, SCLK generator, gated clock and memory. RTL coding is done in verilog. Simulations are observed in MODELSIM simulator and power is calculated by loading the design in Lattice diamond FPGA kit.

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