Architecture of a Floating Point Register for an Experimental RISC CPU

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Author(s) Ajay A. Joshi | Siew Lam | Yee Chan
Pages 868-872
Volume 2
Issue 5
Date May, 2012
Keywords Floating point register, CPU, simulation, algorithm, Floating point unit, VHDL

Abstract

An 8-bit RISC-CPU is designed at gate level using completely custom chip approach. CPU has an 8-bit integer unit and 16-bit floating point unit. The circuits are optimized by using more efficient algorithms. The algorithm discussed in this paper was applied for an 8-bit CPU design, however there is no reason that this couldn't be used for more powerful and serious CPU development. This paper discusses the architecture & design of Floating point register, which includes its VHDL implementation & simulation results as well. Entire project is implemented using VHDL and simulated using Altera MaxPlus II simulation software which can map the design into an Altera CPLD.

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