Design and VLSI Implementation of HDLC Controller

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Author(s) Savita Yadav | Anuradha Yadav | Nishant Tripathi | Sanjay Singh
Pages 1697-1701
Volume 2
Issue 10
Date October, 2012
Keywords HDLC, VLSI, CPU

Abstract

The HDLC Controller MEGACELL is a high performance module for the bit oriented, switched, non-switched packet transmission module. The controller fulfills the specifications according to ITU Q.921, X.25 Level 2 recommendation. It supports half duplex and full duplex communication lines, point-to-point and multipoint channels. The Controller is designed to permit synchronous, code transparent data transmission. The control information is always in the same position and specific bit patterns used for control differ dramatically from those representing data, which reduces the chances of errors. The data stream and transmission rate is controlled from the network node. This eliminates additional synchronization and buffering of the data at the network interface. Some common applications include terminal-to-terminal, terminal to CPU, satellite communication, packet switching and other high-speed data links. In system, which require expensive cabling, and interconnection hardware? So this core can be used to simplify interfacing by going serially, thereby reducing interconnects hardware costs. Since it is speed independent, reducing interconnect hardware could become an important hardware.

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