Design of Reversible Multiplier by Novel ANU Gate

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Author(s) Bhavani Prasad.Y | Rajeev Pankaj.N | Samhitha.N.R | Shruthi.U.K
Pages 354-360
Volume 4
Issue 6
Date June, 2014
Keywords Reversible logic, Nanotechnology, Quantum computing

Abstract

In this paper, a novel Reversible logic gate has been proposed and novel architecture for multiplier is constructed by using proposed gate and Peres gate. For Partial Product Generation RSG Gate is used. This Multiplier gives better results when compared to previous circuits. This novel Gate can be used to design any Boolean logic expression and also any logic gate. The primary characteristics like garbage outputs, Constant inputs and number of gates got decreased. The logical calculations also got decreased. Power dissipation for Reversible logic gates is very less because of its reversibility property. So in present era, reversible logic gates can be used in many applications like bioinformatics, low power CMOS design, optical, quantum computing, DNA computing and also thermodynamic technology, Nanotechnology. The simulation was done in modelsim and synthesis was done by using rc compiler.

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